1 application note 1594 ISL28210SOICEVAL1Z evaluation board user?s guide introduction the ISL28210SOICEVAL1Z evaluation board is designed to evaluate the performance of the isl28210 precision low noise jfet operational amplifier. the isl28210 is a dual jfet amplifier that features low noise, high slew rate, low input bias current and low offset voltage. with a wide operating range from 9v to 40v, in combination with its high precision, low noise and high speed operation, the isl28210 is ideal for precision medical and instrumentation, sensor conditioning, power supply control and photodiode amplifiers. reference documents ? isl28210 data sheet, fn6639 evaluation board key features ? single supply operation: +9v to +40v ? dual supply operation: 4.5v to 20v ? singled-ended or differential input operation ? external vref input ? banana jack connectors for power supply and vref inputs ? bnc connectors for op amp input and output te r m i n a l s ? convenient pcb pads for op amp input/output impedance loading power supplies (figure 1) external power connections are made through the v+, v-, vref, and gnd connections on the evaluation board. the circuit can operate from a single supply or from dual supplies. for single supply operation, the v- and gnd pins are tied together to the negative or ground reference of the power supply. for split supplies, v+ and v- terminals connect to their respective supply terminals. de-coupling capacitors c2 and c4 provide low-frequency power-supply filter ing, while additional capacitors, c3 and c5, which are connected close to the part, filter out high frequency noise. anti-reverse diode d1 (optional) protects the circuit in the momentary case of accidentally reversing the power supplies to the evaluation board. the vref pin can be connected to ground to establish a ground referenced input for split supply operation, or can be externally set to any reference level for single supply operation. figure 1. power supply circuit close to dut 2 0.01f 0.01f 2 1 r31 1 r16 3 2 1 d1 c2 c4 c3 c5 3 2 1 j11 1 j14 1 j12 1 j13 3 2 1 j6 1 j8 0 0 1f 1f vref v+ v- figure 2. precision amplifier with g = -10v/v ina- ina+ r13/r23 isl28210 +4.5v v- v+ 10k 10k - + 100k v ref 100k v out gain = -10v/v to +20v precision sensor -4.5v to -20v r11/r24 r14/r21 r18/r19 inb- inb+ 6 5 1/7 8 4 2 3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. october 1, 2010 an1594.0
2 an1594.0 october 1, 2010 amplifier configuration (figure 3) the schematic of the op amp input stage with the components supplied is shown in figure 3, with a closed loop gain of 10v/v. the differential amplifier gain is expressed in equation 1: for single-ended input with an inverting gain g = -10v/v, the in+ input is grounded and the signal is supplied to the in- input. vref can be connected to a reference voltage between the v+ and v- supply rails. for non-inverting operation with g = 11v/v, the in- input is grounded and the signal is supplied to the in+ input. the non-inverting gain is strongly dependent on any resistance from in- to gnd. for good gain accuracy, a 0 resistor should be installed on the empty r5 pad. user-selectable options (figures 3 and 4) component pads are included to enable a variety of user-selectable circuits to be added to the amplifier inputs, the vref input, outputs and the amplifier feedback loops. a voltage divider (figure 3, r18 and r15) can be added to establish a power supply-tracking common mode reference using the vref input. the inverting and non- inverting inputs have additional resistor placements for adding input attenuation, or to establish input dc offsets through the vref pin. the output (figure 4) also has additional resistor and capacitor placements for filtering and loading. note: operational amplifiers are sensitive to output capacitance and may oscillate. in the event of oscillation, reduce output capacitance by using shorter cables, or add a resistor in series with the output. v out v in+ ( v in- ) r f ( ? r in ) ? ? v ref + = (eq . 1) dnp r5 r4 j2 j1 r1 r2 r14 r18 r15 r13 r11 10k dnp dnp 0 10k dnp 100k open 100k vref to ina - to ina + from v outa c1 in+a in-a figure 3. input stage out a r26 j15 c8 r28 dnp open 0 open c6 v out_a figure 4. output stage table 1. ISL28210SOICEVAL1Z components parts list device # description comments c2, c4 cap, smd, 1206, 1f, 50v, 10%, x7r, rohs power supply decoupling c3, c5 cap, smd, 0603, 0.01f, 50v, 10%, x7r, rohs power supply decoupling c1, c6, c7, c8, c9, c10 cap, smd, 0603, dnp-place hold er, rohs user selectable ca pacitors - not populated d1 40v dual series schottky barri er diode reverse power protection r11, r14, r21, r24 resistor, smd, 0603, 10k , 1%, 1/16w, rohs gain setting resistor r13, r23 resistor, smd, 0603, 100k , 1%, 1/16w, rohs gain setting feedback resistor r1-r3, r5-r8, r10, r12, r15, r17, r20, r22, r28- r30, r32, r34-r36 resistor, smd, 0603, dnp-place holder, rohs user selectable resistors - not populated u1 (isl28210fbz) isl28210fbz, ic prec ision low nosie jfet op amp, soic, rohs application note 1594
3 intersil corporation reserves the right to make changes in circui t design, software and/or specifications at any time without n otice. accordingly, the reader is cautioned to verify that the application note or technical brief is current before proceeding. for information regarding intersil corporation and its products, see www.intersil.com an1594.0 october 1, 2010 application note 1594 ISL28210SOICEVAL1Z top view
4 an1594.0 october 1, 2010 application note 1594 ISL28210SOICEVAL1Z schematic diagram out in+ in- in+ node out in- node close to dut 2 2 1 r29 r26 open 0.01f 0.01f 1 r30 2 j21 1 2 1 r31 1 r16 2 1 j23 2 1 j18 2 1 j24 2 j22 2 1 2 1 j20 2 1 j19 2 1 j17 2 1 r36 1 r32 2 1 r34 2 1 r35 3 2 1 d1 2 1 c1 2 1 r22 2 1 r19 2 1 r21 2 1 r20 21 c10 2 1 r8 2 1 r7 2 1 r5 2 1 r4 2 1 r24 c2 c4 c3 c5 5 4 3 2 1 j15 5 4 3 2 1 j16 5 4 3 2 1 j2 5 4 3 2 1 j1 5 4 3 2 1 j3 5 4 3 2 1 j4 3 2 1 j11 1 j14 1 j12 1 j13 3 2 1 j6 1 j8 2 1 2 1 r27 21 c7 21 c6 21 c8 21 c9 2 1 r1 2 2 1 r25 2 1 r23 2 1 r6 2 1 r17 2 1 r2 2 1 r28 2 1 r14 2 1 r3 2 1 r18 2 1 r15 2 1 r12 2 1 r10 2 1 r13 2 1 r11 8 7 6 5 4 3 2 1 u1 10k 100k 0 0 soic8 dnp 0 dnp open dnp open open 0 dnp dnp dnp dnp open dnp dnp dnp dnp dnp dnp dnp dnp dnp dnp open dnp dnp 10k 100k 100k 10k 10k 0 0 dnp 100k 1f 1f vref vref v+ v- 5 6 7 8 3 4 1 2 generic pack. out a out b in-a in+a in-b in+b
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